1. Field of the Invention
The present invention relates to a structure for improving a performance of transistors of the same type formed in a common chip, and also relates to a method for manufacturing the same.
2. Description of the Background Art
FIG. 32 shows known transistors (conventional N-channel or P-channel transistors), which are of the same type and have different thresholds, and particularly shows a cross section taken along line extending lengthwise through gates. FIG. 32 shows, from the left, transistors having smallest to largest thresholds, i.e., a transistor forming a sense amplifier, a transistor forming a peripheral circuit and a transistor forming a memory cell.
In FIG. 32, a reference number 101 indicates a semiconductor substrate, 102 indicates an LOCOS (Local Oxidation of Silicon) isolating and insulating film, and 103 indicates a heavily doped layer for preventing punch through. A reference number 104 indicates a first impurity layer which is formed at a channel region A in an MIS (Metal Insulator Semiconductor) transistor forming a sense amplifier, and is located at a predetermined depth from a main surface of semiconductor substrate 101. A reference number 105 indicates a second impurity layer which is formed at a channel region B in an MIS transistor forming a peripheral circuit, and is located at a predetermined depth from a main surface of semiconductor substrate 101. A reference number 106 indicates a third impurity layer which is formed at a channel region C in an MIS transistor forming a memory cell, and is located at a predetermined depth from a main surface of semiconductor substrate 101.
In FIG. 32, a reference number 107 indicates a gate insulating film which is formed at the main surface of semiconductor substrate 101 and is made of a silicon oxide film or the like. 108 indicates a gate electrode which is formed on gate insulating film 107, and is made of an electrically conductive film of, e.g., doped polycrystalline silicon. 109 indicates a side wall which is formed of an insulating film on a side surface of gate electrode 109. Reference numbers 110 indicate source/drain regions of an LDD (Lightly Doped Drain) structure formed by diffusing impurity of a conductivity type opposite to that of the channel impurity layer.
First, second and third impurity layers 104, 105 and 106 shown in FIG. 32 are formed at positions spaced from the main surface of semiconductor substrate 101 by predetermined distances depending on only the types of transistors, respectively. The impurity layer for the transistor which should have a larger threshold has a larger impurity concentration, and in other words, the impurity concentration of the impurity layer for the sense amplifier is smaller than that for the peripheral circuit, which is smaller than that for the memory cell. By employing the impurity layers of different impurity concentrations for forming channel regions A, B and C, the thresholds can be controlled such that first impurity layer 104 having a large impurity concentration has a small threshold, and third impurity layer 106 having a small impurity concentration has a large threshold.
FIGS. 33 to 35 show impurity concentration profiles on sections XXXIIIxe2x80x94XXXIII, XXXIVxe2x80x94XXXIV and XXXVxe2x80x94XXXV in FIG. 32 extending downward in a depth direction from the main surface of semiconductor substrate 101 of MIS transistors, respectively. More specifically, FIG. 33 shows an impurity concentration distribution in a depth direction at channel region A in the transistor for sense amplifier. This distribution exhibits a peak provided by first impurity layer 104 and another peak at a deeper position provided by heavily doped layer 103. Likewise, the impurity concentration distributions of the peripheral circuit and the memory cell are shown in FIGS. 34 and 35, respectively. The peak provided by second impurity layer 105 in the peripheral circuit is located at the same depth as first impurity layer 104, and exhibits a larger impurity concentration than that by first impurity layer 104. The peak provided by third impurity layer 106 in the memory cell is located at the same depth as those by first and second impurity layers 104 and 105, and exhibits a larger impurity concentration than those by first and second impurity layers 104 and 105.
For reference purposes, an impurity concentration profile by source/drain region 110 is shown, as an example, in FIG. 35. Since an impurity diffusion layer forming source/drain region 110 is not present immediately under gate electrode 108 in FIG. 32, FIG. 35 shows impurity concentration profiles taken on section XXXVxe2x80x94XXXV extending through source/drain region 110 of the transistor for memory cell in FIG. 32. In FIG. 35, junction is formed at a position where the impurity curve of the channel region intersects the impurity curve of source/drain region 110 of the opposite conductivity type.
A method of manufacturing the above conventional semiconductor device will be described below. First, as shown in FIG. 36, thermal oxidation is effected to form LOCOS isolating and insulating film 102 on each region which will form an inactive region in P-type semiconductor substrate 101. Then, wells are formed by selectively ion-implanting ions into regions for forming the N-type transistors under conditions of 500 KeV and 5E12 cmxe2x88x922. Thereafter, selective ion-implantation of, e.g., boron is performed under conditions of 100 KeV and 5E12 cmxe2x88x922 to form heavily doped layer 103 for isolation immediately under each LOCOS isolating oxide film 102. simultaneously with this, heavily doped layers 103 are formed under channel regions A, B and C.
Then, as shown in FIG. 37, boron is ion-implanted into the whole surface of semiconductor substrate 101 under conditions of 50 KeV and 2E12 cmxe2x88x922, whereby first impurity layer 104 of the transistor for sense amplifier is formed. Simultaneously with the formation of first impurity layer 104, first impurity layers 104 are formed at channel regions B and C of the transistors for peripheral circuit and memory cell.
As shown in FIG. 38, a resist pattern 111 is formed over the regions for transistors of a different type (P-channel transistors), the region of the transistor for sense amplifier and LOCOS isolating and insulating films 102 around the same, and boron is implanted into the regions for transistors for the peripheral circuit and memory cell under conditions of 50 KeV and 3E12 cmxe2x88x922. Further, impurity is implanted into channel region B of the peripheral circuit to form second impurity layer 105 having a larger impurity concentration than first impurity layer 104. Thereby, channel region C of the transistor for memory cell has the same concentration as second impurity layer 105.
As shown in FIG. 39, a resist pattern 112 is formed over regions other than the region for forming the transistor for memory cell. Using resist pattern 112 as a mask, ion implantation of boron is performed under conditions of 50 KeV and 2E12 cmxe2x88x922 for additionally introducing impurity into channel region C, so that third impurity layer 106 having a larger impurity concentration than second impurity layer 105 is formed.
In the conventional manufacturing method, as described above, first, second and third impurity layers 104, 105 and 106 are formed in the following manner. Ion implantation is performed several times for the heavily doped layer(s), and is performed one (or two) time(s) for the lightly doped layer(s), and all of the first and succeeding ion implanting operations are effected on positions at the same depth with the same implantation energy.
Japanese Patent Laying-Open No. 2-153574 (1990) has disclosed a technique similar to the above, and more specifically has disclosed the following technique. In transistors which have different thresholds but are of the same type, channel impurity layers having different impurity concentrations are formed at the same depth from a main surface of a semiconductor substrate. For forming causing a difference in impurity concentrations of the channel impurity layers, implantation is performed several times on a channel portion (at the same position) of a transistor(s) to be doped heavily.
According to the above structure, however, it is now required to increase impurity concentration for suppressing punch through, because channel lengths of transistors have been reduced in accordance with miniaturization of elements. Therefore, if channel implanting operations for three regions for the sense amplifier, peripheral circuit and memory cell were performed with the same energy, impurity concentrations would unpreferably increase at transistor surfaces of the regions for the sense amplifier and peripheral circuit, so that thresholds would unpreferably increase. In addition to this, since the impurity concentration is large at the channel region in the region for memory cell, the concentration is large at the junction between the source/drain region and the channel region, so that an excessively strong junction electric field is produced, and a junction leakage current increases.
An object of the invention is to provide a semiconductor device, in which transistors can have a low threshold while preventing punch through and a junction electric field with respect to source/drain regions can be restricted, and a method of manufacturing the same.
For achieving the above object, an aspect of the invention provides a semiconductor device, in which first and second MIS transistors of the same conductivity type are formed at a main surface of a semiconductor substrate, impurity concentration profiles on sections extending through channel regions of the first and second MIS transistors in a depth direction from the main surface of the semiconductor substrate have peaks at different depths.
According to the above structure, the two transistors on a common chip have the channel regions provided with the impurity layers, of which impurity concentrations have peaks at different peaks, so that thresholds of the transistors can be controlled, and thus each transistor can be optimized.
In a semiconductor device of another aspect of the invention, first and second MIS transistors of the same conductivity type are formed at a main surface of a semiconductor substrate, the first MIS transistor has a first channel region provided with a first impurity layer, the second MIS transistor has a second channel region provided with a second impurity layer, the second MIS transistor has a higher threshold voltage than the first MIS transistor, and the first impurity layer is formed at a position deeper from the main surface than the second impurity layer.
According to this structure, the channel regions of the two transistors formed on a common chip are provided with the impurity layers at different depths, so that thresholds of the transistors can be controlled, and thus each transistor can be optimized.
In the semiconductor device having the above structure, it is preferable that at least one of impurity concentration profiles at the first and second channel regions in the depth direction from the main surface has at least two peak values. By this structure, the transistor can suppress a low surface impurity concentration at the channel region and can have a low threshold.
In the semiconductor device of the above structure, it is preferable that the first and second impurity layers have different kinds of impurity. According to this structure, an impurity concentration distribution at a specified channel region can be controlled steeply. Therefore, a concentration at a junction between the source/drain region and the channel region can be low, so that a resistance against punch through can be improved and junction leakage can be suppressed.
In a semiconductor device of still another aspect of the invention, first, second and third MIS transistors of the same conductivity type are formed at a main surface of a semiconductor substrate, the first, second and third MIS transistors form a sense amplifier, a peripheral circuit and a memory cell, respectively, and impurity concentration profiles extending in a depth direction from the main surface through channel regions of the first, second and third MIS transistors have peaks at different depths, respectively.
Owing to the above structure, thresholds of the first, second and third MIS transistors can be controlled to take on values required in the sense amplifier, peripheral circuit and memory cell, respectively, so that the transistors can have characteristics optimized for their purposes, respectively.
In a semiconductor device of yet another aspect of the invention, first and second MIS transistors of the same conductivity type are formed at a main surface of a semiconductor substrate, the first and second MIS transistors have first and second channel regions, respectively, the first channel region is provided with a first heavily doped layer at a predetermined depth from the main surface, and the second channel region is provided with a second heavily doped layer at the substantially same depth as the first heavily doped layer from the main surface and is provided with an impurity layer between the second heavily doped layer and the main surface.
Owing to the above structure, a heavily doped layer common to the first and second channel regions can be formed at a relatively deep position for using the same for channel cut and threshold control of the first or second MIS transistor. In addition to the heavily doped layer, the second channel region is provided with the impurity layer at a position shallower than the heavily doped layer, whereby the threshold can be controlled further precisely.
In a preferred embodiment of the invention, the impurity layer formed at the second channel region has a plurality of layers formed at different depths between the second heavily doped layer and the main surface. This structure enables more precise and desirable distribution of impurity concentration in a depth direction.
In another preferred embodiment of the invention, impurity contained in the first and second heavily doped layers is made of a substance different from that of impurity contained in the impurity layer. Since the second heavily doped layer and the impurity layer in the second channel region have the impurity layers containing different kinds of impurity, the impurity concentration distributions can be selectively set steep. Consequently, a concentration at a junction between the source/drain region and the channel region can be low, so that a resistance against punch through can be improved and junction leakage can be suppressed.
A method of manufacturing a semiconductor device of an aspect of the invention, and particularly forming, at a main surface of a semiconductor substrate, a first MIS transistor having a first channel region and a second MIS transistor having a second channel region, includes the steps of: forming first and second active regions at the main surface of the semiconductor substrate for forming the first and second MIS transistors, respectively; forming the first channel region having a first impurity layer by implanting ions with a predetermined ion implanting energy into a region for the first channel region in the first active region; forming the second channel region having a second impurity layer by implanting ions with an ion implanting energy different from the predetermined ion implanting energy into a region for the second channel region in the second active region; forming a gate insulating film on the first and second channel regions; forming gate electrodes on the first and second channel regions with the gate insulating film therebetween, respectively; and forming source/drain regions at positions in the main surface located at opposite sides of each of the first and second channel regions.
According to this manufacturing method, the first and second impurity layers for the first and second MIS transistors are formed by ion implantation at different steps, so that the channel regions can have impurity concentration profiles optimized for the transistors, respectively. Consequently, it is possible to fabricate the semiconductor device having the transistors of the optimum characteristics.
In a preferred embodiment of the invention, the steps of forming the first and second channel regions are performed by ion implantation with different ion implanting energies or of different ion species. Thereby, impurity profiles at the channel regions can be controlled individually, so that it is possible to optimize characteristics of the first and second MIS transistors having different thresholds.
A method of manufacturing a semiconductor device of another aspect of the invention, and particularly forming, at a main surface of a semiconductor substrate, a first MIS transistor having a first channel region and a second MIS transistor having a second channel region includes the steps of: forming, at the main surface of the semiconductor substrate, first and second active regions for forming the first and second MIS transistors, respectively; forming first and second heavily doped layers by effecting ion implantation with a predetermined ion implanting energy on regions for the first and second channel regions in the first and second active regions, respectively; forming, at a region for the second channel region in the second active region, an impurity layer located between a position for forming the second heavily doped layer and the main surface; forming a gate insulating film on the first and second channel regions; forming gate electrodes on the first and second channel regions with the gate insulating film therebetween; and forming source/drain regions at positions in the main surface located at opposite sides of each of the first and second channel regions.
According to the above method of manufacturing the semiconductor device, the impurity layer can be selectively formed and located between the main surface of the second channel region of the second transistor and the second heavily doped layer, whereby the thresholds can be controlled to attain optimum values, and an effect of channel cut can be expected in the semiconductor device.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.